The present invention relates generally to a complex arithmetic vector processor (CAVP), particularly for use in a hierarchical multiprocessor system (HMS) using very high speed integrated circuit (VHSIC) chips in microprogrammed modules.
U.S. patents showing the state of the art include U.S. Pat. No. 3,900,723 to Bethany et al which discloses an apparatus for controlling the arithmetic units of a computer pipeline to accomplish arithmetic operations on a plurality of operand vectors to derive resultants. U.S. Pat. No. 4,172,287 to Kawabe et al discloses a data processing apparatus for processing vector instructions at very high speeds. U.S. PAt. No. 3,541,516 to Senzig discloses a vector arithmetic multiprocessor computer system which operates on vector arithmetic problems in which identical operations are to be performed substantially simultaneously upon a plurality of different units of data. U.S. Pat. No. 4,128,876 to Ames et al discloses an interface comprising asynchronous I/O interface hardware in combination with additional synchronizing connections between a microcoded central processing unit and a microcoded secondary processor. U.S. Pat. No. 3,794,984 to Deerfield et al discloses a digital computer adapted to perform vector and matrix operations.